1. Field of the Invention
The invention disclosed herein is related to automatically routing paths for interconnections between terminals of interoperable components. More specifically, the invention is related to providing to an automatic circuit router, or “autorouter”, guidance to route associated interconnections along a user-specified common path.
2. Description of the Prior Art
In the early days of Printed Circuit Board (PCB)/Package design, manual layout tools and terminal interconnection methods were adequate to fully provide the geometrically defined interconnection paths between terminals of a circuit. These simple solutions to the “interconnect problem” were achievable due to the small number of interconnections in the circuits, simple circuit layouts and that registration of artwork required only moderate precision. As component feature sizes became smaller, the scope of the interconnect problem in terms of connection count and layout complexity grew to a point where manual methods no longer suffice. Computer-aided Design (CAD) tools were introduced at that time to assist designers in realizing more complicated designs, albeit still manually. In the CAD systems, each interconnect pattern was interactively created with a toolset provided by a user interface.
Routing engines were then introduced to at least partially automate the creation of the interconnect pattern, thereby relieving the designer of some of the tedious interconnection tasks. However, circuit design and manufacturing technologies continued to outpace advances in routing engine technology. Technological advances leading to higher operating frequencies, faster logic architectures, and longer and wider data paths necessitated stricter design constraints that were beyond the capabilities of the available routing engines. Thus, the most difficult and most challenging designs continued to be routed manually, with a designer interactively selecting the exact path vertex-by-vertex for each connection. Then, when an Engineering Change Order (ECO) was issued, extensive manual editing would often be required, particularly when many connections had to be retuned to meet established delay constraints. In such cases, the long period of time devoted to the design phase severely delayed the introduction of new products to the marketplace.
Recent years have seen unprecedented expansion of functional requirements for PCB designs. PCB designers must now cope with a myriad of interconnect topologies and logic signal levels, and must be constantly keen to tolerance stack-up and to implications to signal integrity of an evolving placement/interconnect solution. Designers must balance dozens of variables that may resolve into hundreds of valid and invalid solutions without any real guidance from the available tools toward selecting the best solution. Electronic Design Automation (EDA) customers have responded to these shortcomings by demanding more route engine power, interactive functionality and diverse capabilities from their CAD tools.
Currently, users solve difficult routing problems interactively through a manual CAD editing environment according to a tedious manual process. Certain connections are selected, some portion of the path for these connections is routed, problems are located and resolved, and the process is iterated until done. This is an extremely slow and arduous process and, because the PCB design is typically the last stage in the production of a new product, time-to-market for the entire product is adversely affected.
Traditionally, PCB autorouters have allowed the user only limited control over the routing process and limited ability to influence autorouting decisions. There have been some mechanisms by which users may force certain paths to be preserved or to restrict routing to certain regions. It is quite apparent, though, that as PCB complexity continues to soar, more and more designs will be beyond the limit of the current generation of autorouting tools.
Before routing a PCB in detail, designers first develop a mental model of how the interconnect problem should ultimately be solved. This process can take weeks or months, as experiments with different topologies are conducted and signal integrity engineers are consulted, adjusting accordingly the set of electrical design constraints. Their mental concept or vision is considered their routing strategy or plan and, although sometimes sketched out on paper, must remain in focus by the designer throughout the routing process. But, because this mental planning information cannot be conveyed to the autorouter, it is extremely unlikely that the autorouter would produce the solution that follows the design team's plan. An effective approach to capture the planning data electronically to incorporate it into the design database is heretofore unknown. Having no alternative, PCB designers are then forced to manually route the entire design. This additional work can add several weeks or months to the product development process.
Modern autorouters are not without some limited mechanisms for displaying dedicated connections and controlling certain interconnection routes. Schematics tools, for example, have long implemented a “bus”, i.e., a set of related conductors that are graphically treated as one. For example, one line on the user interface labeled “addr[63:0]” could graphically represent an entire 64-bit bus. This allows the electrical designer to focus on the schematic interconnect at a higher level of abstraction without being overwhelmed by details. While this has worked well in schematics, the concept has not been extended to control an autorouter. Moreover, because the locations on a schematic typically have no relationship to locations on a PCB, the bus concept does not translate well into the layout regime.
Some PCB layout tools have included certain graphical features, such as a “fat rat”, where two or more related connections between the same two components are displayed as one line. However, such tools have merely been used for the graphical display of unrouted connections and have not been provided to an autorouter to control routing.
Other EDA toolsets of the prior art have included “multi-plow” functionality that allows several interconnections to be routed together. The user interactively selects several interconnections and manually routes them as a group. Traditionally, this is achieved by pointing to a location in the layout with an indicating device and the autorouter then attempts to route all selected wires to that location. However, these systems have failed to provide planning features or data retention. That is to say, once the plow action is completed, no information about the selected interconnections or about the guided location is stored. Thus, any modification to the design, even if the routes need only to be “tweaked”, requires that the process has to begin all over again.
Several prior art PCB layout tools have implemented a “hug” feature, where the user manually routes one interconnection and other interconnections are automatically routed to follow the original interconnection's path. However, nothing is retained by the autorouter for future use. For example, there is no association maintained between the guiding path and the follower paths. If the autorouter is started after this process is completed, the user-created pattern is destroyed.
The present technology continues to fall short of meeting the needs of the designer. Without a means of conveying to the route engine what is in the mind of the designer, the designer must ultimately perform the routing tasks manually. The designer is left in the position of “hoping” that their best guess is the correct one. Current tools do not provide a way to conceptualize the problem, let alone resolve it, visualize it or quickly assess whether a potential solution is good or bad. Moreover, in that a design plan cannot be realized without consideration of all constraints, the designer is left to interpret and reconcile problems as they manually route.
The need is apparent for a toolset that allows the router to automatically perform the tedious routing tasks, while at the same time allowing the designer to influence the solution interactively by inputting their design intent into the design. Data abstraction should be implemented to allow data manipulation and storage of the designer's plan. Such tools should also make possible recognition of patterns in the data within the design and to bundle the data together. It should allow the designer to visualize these patterns so as to develop a high level view or a flow plan, while verifying the integrity of this solution as it develops. It should also, of course, convert the data abstraction into a real interconnect pattern through a routing engine that operates on the abstraction to verify the routing solution and instantiate it correctly.